The invention relates generally to a read pre-charge level of SRAM cells, and more specifically, to memory cell arrangements of SRAM cell groups. The invention relates further to a related design structure.
SRAM cells are often arranged in a domino-logic structure in which two or more SRAM (static random access memory) cells are connected in parallel to local bit-lines. An amplifier between local bit-lines and a shared global bit-line helps to separate the local bit-lines from the global bit-line. Typically, both, the local and the global bit-lines may be pre-charged high before a read operation, and may be discharged, or “pulled-down,” to ground during a read operation. This may enable a higher read rate than detecting the status of the global bit-line directly. A particular cell may be selected for reading by activating the cell's word line. If the discharged local bit-line is the one that is coupled to the global bit-line, a discharge of the local bit-line may activate logic that discharges the global bit-line.
Using this mechanism for detecting a status of a SRAM cell, it may not be required to pre-charge a local bit-line and/or a global bit-line to the full amount of Vdd (also known as the power supply voltage). In other words, a full swing pre-charge may not be required.
Other documents have been dealt with this area. E.g., U.S. Pat. No. 8,947,970 B2 discloses “a memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted.”
US Patent Application 2010/0296354-A1 discloses a static random access memory which includes “a memory cell connected to a pair of bitlines and supplied with the power supply voltage from a first power supply[,] a pre-charge circuit connected with the pair of bitlines . . . and a voltage reducing circuit connected between the precharge circuit and the first power supply.”
However, a problem related to the global bit-line remains. The global bit-lines build an intrinsic capacitor. Because a plurality of the above-mentioned amplifiers may be connected to the global bit-line, the global bit-line requires a lot of pre-charging power during a read operation of SRAM cells. As the SRAM cell may be pre-charged in a first phase of a read operation and discharged in an evaluation phase, depending on the SRAM cells content, about 50% of global bit-lines are charged and/or discharged during every memory cycle. A power equivalent to the operation frequency times the effective capacitor of the global bit-lines times the power supply voltage (Vdd) times the pre-charge voltage may be required. This may contribute enormously to the power consumption of an SRAM array. Because SRAM cells are often used as level-1 or level-2 caches in processors, the power consumption of these SRAM arrays contributes significantly to the power consumption of the processor.
Hence, there may be a need for a reduction of the amount of power required to pre-charge the global bit-lines in the first phase of a read operation.